Power up reset generators are known in order to monitor the evolution of a power supply to a circuit during power up. As the power supply voltage increases, logic elements in the circuit may latch into ill-defined and undesirable states. It is therefore known to provide a reset signal as soon as the power supply has become sufficiently established such that the circuit can start from a known initial condition, or to keep a reset signal in an active state until the power supply has reached a minimum acceptable value.
Power up reset circuits are known, for example, in US 2012/0117410 where, as described in its abstract, a current mirror is configured to supply a first current to a first line and a second current to a second line, and a comparator voltage generator is configured to generate a voltage using the first current provided by the first line. A driver is connected to the second line and configured to activate a reset signal in response to a voltage on the second line. A ground selecting transistor is further arranged to connect the second line and the ground line together in response to the comparator voltage. A problem with such a circuit is that it draws current through both limbs of the current mirror once the supply voltage has become established and, since the power up reset circuit is continuously on, is an unnecessary waste of power.